Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. Notably, as used herein, “include” and “including” mean including without limitation.
One such FPGA is the Xilinx Virtex™ FPGA available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. Another type of PLD is the Complex Programmable Logic Device (“CPLD”). A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, for example, using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
For purposes of clarity, FPGAs are described below though other types of PLDs may be used. FPGAs may include one or more embedded microprocessors. For example, a microprocessor may be located in an area reserved for it, generally referred to as a “processor block.”
In a Direct Digital Synthesizer (“DDS”) or a Numerically Controlled Oscillator (“NCO”), conventionally a sequence of numbers describing a value of a sinusoid wave are generated using a look-up table of values. The sequence of numbers is a sequence of phase values or phase increments. A phase accumulator is used to accumulate phase increments to generate a phase slope signal. The phase slope signal may be adjusted by a phase offset or dither noise, or a combination of both phase offset and dither noise.
Conventionally, substantially fine frequency resolution is implemented for a DDS or an NCO. The degree of frequency resolution is conventionally associated with the depth of the look-up table, as well as the data width of the phase slope signal generated. Even though the phase slope signal may be quantized, where only Most Significant Bits (“MSBs”) of the phase slope signal are used to provide an address to a look-up table, this quantization occurs after phase accumulation. Thus, a significantly large number of bits may be used for a phase accumulation stage which is positioned prior to a quantization stage.
For implementing a phase accumulator, a carry chain in a phase accumulator adders stage may be significantly lengthy owing to the number of bits used to obtain a desired frequency resolution. The length of such a carry chain may thus be a speed limiting path, and may even be a “critical path”, of a DDS or an NCO.
Accordingly, it would be desirable and useful to provide means for reducing the impact of delay associated with phase accumulation.